1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device and to semiconductor device structures. Particularly, the present invention relates to forming shaped FinFETs, shaping formed fins and to semiconductor device structures having shaped fins.
2. Description of the Related Art
Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors, represent the core building blocks for a vast majority of semiconductor integrated circuits. Generally, a FET includes source and drain regions between which a current flow is controlled by applying a bias to a gate electrode overlying a channel region between the source and drain regions. Conventional integrated circuits (ICs), such as high-performance microprocessors for example, may include a great number of FETs, usually on the order of millions. For such ICs, decreasing transistor size and, therefore, increasing integration density, has traditionally been a high priority in the semiconductor manufacturing industry. Nevertheless, transistor performance must be maintained with decreasing transistor size.
A FinFET is a type of transistor that addresses reducing the transistor size while maintaining transistor performance. In general, FinFETs represent three-dimensional transistors formed by thin fins extending upwardly from a semiconductor substrate. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, which is also frequently referred to as a double gate transistor, or along the vertical sidewall surfaces and the upper horizontal surface of the fin, leading to a so-called tri-gate transistor. Double gate transistors and tri-gate transistors have a wide channel and, hence, high performance, which can be achieved without substantially increasing the area of the substrate surface required by the transistors because a transistor's performance, often measured by its transconductance, is proportional to the width of the transistor channel.
As opposed to planar MOS transistors, which are well known in the art and so their features need not be explained, FinFETs are less well known, so that the following brief explanations with regard to FIGS. 1a and 1b are provided to briefly discuss known FinFET structures.
FIG. 1a illustrates, in a cut-away perspective view, a portion of a FinFET integrated circuit (IC) 100a. The illustrated portion of IC 100a includes two fins 102a and 104a that are formed from a bulk semiconductor substrate 106a and extend upwardly therefrom. A gate electrode 108a overlies the two fins 102a and 104a and is electrically insulated from the fins 102a, 104a by a gate insulator (not illustrated). One end (denoted by 110a) of the fin 102a may be appropriately impurity doped to form the source of a field effect transistor (FET) 112a, while the other end (denoted by 114a) of that fin may be appropriately impurity doped to form the drain of the FET 112a. Similarly, ends 116a and 118a of the fin 104a may form the source and drain of another FET 120a. The illustrated portion of IC 100a thus includes two FinFETs 112a and 120a having a common gate electrode. In another configuration, if source 110a and source 116a are electrically coupled together and drain 114a and drain 118a are electrically coupled together, the structure would be a two-fin FinFET having twice the gate width of either FinFET 112a or 120a. An insulating layer 122a, such as an oxide or nitride layer, provides electrical isolation between the fins 102a, 104a and between adjacent devices as is needed for the circuit being implemented.
The channel of the FinFET 112a extends along a sidewall 124a of the fin 102a beneath the gate electrode 108a, along the top 125a of the fin, as well as along an opposite sidewall of the fin 102a which is not visible in this perspective view. The advantage of the FinFET structure is that, although the fin 102a has only the narrow width represented by arrows 126a, the channel has a width represented by at least twice the height of the fin above the oxide 122a. In general, the channel width can be greater than the fin width.
In the example described with regard to FIG. 1a, the source and drain regions are formed within each of the fins 102a, 104a. The common gate electrode 108a overlying the fins 102a, 104a defines the channel region of the respective fins, while a continuous isolation layer 122a is provided in trenches which delineate and partially embed the fins, except for the portion of the fins over which the gate electrode 108a is formed, thereby adjusting an effective height of the fins.
FIG. 1b schematically illustrates a perspective view of another FinFET integrated circuit (IC) 100b corresponding to a three-dimensional transistor configuration or tri-gate transistor configuration. As illustrated, corresponding semiconductor fins 110b may be provided in an active region 101b in combination with a dielectric material 106b. An effective fin height is adjusted by the amount or height of the dielectric material 106b which is filled in between the semiconductor fins 110b. 
For forming the IC 100b, a gate opening 120b is provided within a gate electrode structure formed above the active region 101b, wherein the gate electrode structure comprises a spacer structure 122b. Then, a masking pattern is formed within the gate opening in accordance with the fins 110b to be fabricated. After having formed the fins 110b, a gate electrode may be formed by depositing a gate dielectric layer on the exposed surface areas of the active region 101b in the gate opening 120b and, particularly, on exposed surfaces of the fins 110b. The gate opening 120b, as depicted in FIG. 1b, therefore represents the gate electrode, which is omitted for the sake of a clear perspective illustration of IC 100b in FIG. 1b. 
In accordance with the spacer structure 122b, source regions 110bS and drain regions 110bD are formed in the active region 101b at respective ends of fins 110b. In the IC 100b depicted in FIG. 1b, the source regions 110bS and the drain regions 110bD are not constituted by the fins 110b and, in particular, the source and drain regions are not formed within the fins 110b. 
FIG. 1b further depicts a contact layer 140b with a stress-inducing layer 141b for enhancing mobility properties of charge carriers within the channel regions and another dielectric layer 142b formed over the stress-inducing layer 141b. 
Recently, FinFETs have been considered as representing important candidates for next generation transistors at 22 nm and beyond technologies. Opposed to conventional planar FET configurations, FinFETs allow for more effective suppression of “off-state” leakage currents because the channel is surrounded by several gates on the multiple surfaces of the fins. For this reason, multiple gate configurations are considered as to allow enhanced current in the “on” state of according transistors, also known as drive currents, such that power consumption of nonplanar FETs are expected to be further lowered and device performance to be further enhanced as compared to conventional planar FETs.
When considering FinFET technologies, further technological integration challenges arise. For example, it turns out that conformal deposition of particularly thin layers on the fins becomes more difficult to achieve on surfaces of current fins, particularly on vertical surfaces of the fins. Furthermore, it becomes more difficult to perform implantation processes for sufficiently adjusting required doping profiles in present fins because implanting into the vertical surfaces of scaled fins is intriguingly difficult to achieve. Therefore, the thicknesses of high-k material layers and metal gate layers deposited on the surfaces of fins, as well as required doping profiles within fins, cannot be sufficiently well controlled for modern scaled FinFET structures. Strong shifts in the threshold voltage and increased gate leakage arise, resulting in ICs which do not satisfy present quality requirements.
Therefore, it is desirable to provide methods for allowing a more stable and robust fabrication process when fabricating ICs having FinFET structures. It is further desirable to provide semiconductor devices satisfying present quality requirements, and particularly for FinFETs having less variability in their electrical device parameters. Particularly, it is desirable to provide methods and semiconductor device structures which enable better deposition coverage at thin layer deposition processes on fins and/or formation of a reliable dopant profile within fins.